I. Field of the Disclosure
The technology of the disclosure relates generally to monolithic three dimensional (3D) integrated circuits (IC) (3DIC).
II. Background
Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. The limited space contributes pressure to a continued miniaturization of components and power consumption within the circuitry. While miniaturization has been of particular concern in the integrated circuits (ICs) of mobile communication devices, efforts at miniaturization of ICs in other devices have also proceeded.
Historically, elements within an IC have all been placed in a single two dimensional active layer with elements interconnected through one or more metal layers that are also within the IC. Efforts to miniaturize are reaching their limits in a two dimensional space and thus, design thoughts have moved to three dimensions. While there have been efforts to connect two or more ICs through a separate set of metal layers outside the IC proper, that solution is not properly a three dimensional (3D) approach. Likewise, two IC chips have been stacked one atop another with connections made between the two IC chips through solder bumps (i.e., the so called “flip chip” format). Likewise, there are system in package (SIP) solutions that stack IC chips atop one another with connections made between the chips with through silicon vias (TSVs). While arguably the flip chip and TSV embodiments represent 3D solutions, the amount of space required to effectuate a flip chip remains large. Likewise, the space required to implement a TSV relative to the overall size of the chip becomes space prohibitive.
In response to the difficulties in effectuating small ICs that meet miniaturization goals, the industry has introduced monolithic three dimensional ICs (3DICs). The advent of monolithic 3DIC has provided a number of interesting possibilities in circuit design, but creates its own design issues. In particular, process variations between layers or tiers of the 3DIC may result in unacceptable clock skew with very large 3-sigma spread. When such skewed clock signals are applied to flip-flops, this clock skew may result in unacceptable setup times, hold times, or clock-to-q margins. The skew introduced by the process variations may further be aggravated by the software that automatically performs chip layout design.